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| author |   Dan Carpenter <dan.carpenter@linaro.org> | 2024-07-17 21:25:53 -0500 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2024-07-18 13:33:15 -0700 |
| commit | 5a6a25ea5bcd5bdf80fb13acd65a03fc6b8794b1 (patch) | |
| tree | c1521c86577a05b336bf4f2f1d2375e792d5753b /scripts/generate_rust_analyzer.py | |
| parent | clk: davinci: da8xx-cfgchip: Initialize clk_init_data before use (diff) | |
| download | wireguard-linux-5a6a25ea5bcd5bdf80fb13acd65a03fc6b8794b1.tar.xz wireguard-linux-5a6a25ea5bcd5bdf80fb13acd65a03fc6b8794b1.zip | |
clk: sophgo: clk-sg2042-pll: Fix uninitialized variable in debug output
If sg2042_get_pll_ctl_setting() fails then "value" isn't initialized and
it is printed in the debug output. Initialize it to zero.
Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/baf0a490-d5ba-4528-90ba-80399684692d@stanley.mountain
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions