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| author |   Chen Wang <unicorn_wang@outlook.com> | 2024-01-31 09:57:01 +0800 |
|---|---|---|
| committer | Chen Wang <unicorn_wang@outlook.com> | 2024-06-14 14:49:40 +0800 |
| commit | 5a7144d61d73d801540f8846d8e1b9fa52a5559c (patch) | |
| tree | 77f87eb5c2e1ced31fc41ec7237a1a4eee68bdcc /scripts/generate_rust_analyzer.py | |
| parent | dt-bindings: clock: sophgo: add pll clocks for SG2042 (diff) | |
| download | wireguard-linux-5a7144d61d73d801540f8846d8e1b9fa52a5559c.tar.xz wireguard-linux-5a7144d61d73d801540f8846d8e1b9fa52a5559c.zip | |
dt-bindings: clock: sophgo: add RP gate clocks for SG2042
Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions