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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-12-07 16:47:34 +0100 |
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| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-12-07 16:47:34 +0100 |
| commit | 5ca77c9d80d3e5e3dec27217e580195f09ca4673 (patch) | |
| tree | 6a11ea0d790304d88cf328f2f7e2c5d867a8a172 /scripts/generate_rust_analyzer.py | |
| parent | soc: renesas: rcar-gen4-sysc: Introduce R-Car Gen4 SYSC driver (diff) | |
| parent | dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions (diff) | |
| download | wireguard-linux-5ca77c9d80d3e5e3dec27217e580195f09ca4673.tar.xz wireguard-linux-5ca77c9d80d3e5e3dec27217e580195f09ca4673.zip | |
Merge tag 'renesas-r8a779f0-dt-binding-defs-tag' into renesas-drivers-for-v5.17
Renesas R-Car S4-8 DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car S4-8 (R8A77FA0)
SoC, shared by driver and DT source files.
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions