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| author |   Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> | 2022-08-24 15:47:26 +0300 |
|---|---|---|
| committer |   Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2022-09-07 23:48:42 +0300 |
| commit | 603c8e130d06fc70e84c9704d74c69f098975453 (patch) | |
| tree | c81c0bdee2b15c3edfe92c4f60412884c4200a00 /scripts/generate_rust_analyzer.py | |
| parent | drm: rcar-du: Fix DSI enable & disable sequence (diff) | |
| download | wireguard-linux-603c8e130d06fc70e84c9704d74c69f098975453.tar.xz wireguard-linux-603c8e130d06fc70e84c9704d74c69f098975453.zip | |
drm: rcar-du: dsi: Fix VCLKSET write
rcar_mipi_dsi_startup() writes correct values to VCLKSET, but as it uses
or-operation to add the new values to the current value in the register,
it should first make sure the fields are cleared.
Do this by using rcar_mipi_dsi_write() to write the VCLKSET register
with a variable that has all the unused bits zeroed.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions