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| author |   Peng Fan <peng.fan@nxp.com> | 2023-04-03 17:53:00 +0800 |
|---|---|---|
| committer |   Abel Vesa <abel.vesa@linaro.org> | 2023-04-09 16:48:54 +0300 |
| commit | 6b60c3ae3e98d036945f2d5c11d35b4c178ea423 (patch) | |
| tree | e729b0b9c199b41f9e2eb8115b3996e35c50d912 /scripts/generate_rust_analyzer.py | |
| parent | dt-bindings: clock: imx93: add NIC, A55 and ARM PLL CLK (diff) | |
| download | wireguard-linux-6b60c3ae3e98d036945f2d5c11d35b4c178ea423.tar.xz wireguard-linux-6b60c3ae3e98d036945f2d5c11d35b4c178ea423.zip | |
clk: imx: imx93: Add nic and A55 clk
The A55 clock logic as below:
A55_PLL ----------------->\
A55_SEL-->A55_CORE
A55_CCM_ROOT--->A55_GATE->/
Add A55 CPU clk to support freq change.
Add NIC CLK to reflect the clk status
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230403095300.3386988-8-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions