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| author |   Kuldeep Singh <singh.kuldeep87k@gmail.com> | 2022-03-12 17:08:52 +0530 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2022-08-19 10:51:13 +0200 |
| commit | 6c939e28b192075e1d3b9b267100a3dd9d6a7cf7 (patch) | |
| tree | 1a7bbb8cd7d4758234764b3235265201b4d13b86 /scripts/generate_rust_analyzer.py | |
| parent | ARM: dts: realview: Update spi clock-names property (diff) | |
| download | wireguard-linux-6c939e28b192075e1d3b9b267100a3dd9d6a7cf7.tar.xz wireguard-linux-6c939e28b192075e1d3b9b267100a3dd9d6a7cf7.zip | |
ARM: dts: versatile: Update spi clock-names property
Now that spi pl022 binding only accept "sspclk" as clock name, versatile
platform with "SSPCLK" clock name start raising dtbs_check warnings.
Make necessary changes to update this property in order to make it
compliant with binding.
clock-names:0: 'sspclk' was expected
Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Link: https://lore.kernel.org/r/20220312113853.63446-4-singh.kuldeep87k@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions