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| author |   Vincent Chen <vincent.chen@sifive.com> | 2022-03-08 16:32:53 +0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-03-22 14:45:19 -0700 |
| commit | 6d1a6f464efd596779d1b272b3dc8170c5fa189f (patch) | |
| tree | 35f6444e6bae8e031bcefcb457bd0de3ebbfe16a /scripts/generate_rust_analyzer.py | |
| parent | RISC-V: Add support for restartable sequence (diff) | |
| download | wireguard-linux-6d1a6f464efd596779d1b272b3dc8170c5fa189f.tar.xz wireguard-linux-6d1a6f464efd596779d1b272b3dc8170c5fa189f.zip | |
rseq/selftests: Add support for RISC-V
Add support for RISC-V in the rseq selftests, which covers both
64-bit and 32-bit ISA with little endian mode.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Tested-by: Eric Lin <eric.lin@sifive.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions