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| author |   Nikunj A Dadhania <nikunj@amd.com> | 2025-01-06 18:16:30 +0530 |
|---|---|---|
| committer |   Borislav Petkov (AMD) <bp@alien8.de> | 2025-01-08 21:26:19 +0100 |
| commit | 73bbf3b0fbba9aa27fef07a1fbd837661a863f03 (patch) | |
| tree | 5aed0ee86cb776b621cf53b4c98239f2997a1080 /scripts/generate_rust_analyzer.py | |
| parent | x86/sev: Mark the TSC in a secure TSC guest as reliable (diff) | |
| download | wireguard-linux-73bbf3b0fbba9aa27fef07a1fbd837661a863f03.tar.xz wireguard-linux-73bbf3b0fbba9aa27fef07a1fbd837661a863f03.zip | |
x86/tsc: Init the TSC for Secure TSC guests
Use the GUEST_TSC_FREQ MSR to discover the TSC frequency instead of
relying on kvm-clock based frequency calibration. Override both CPU and
TSC frequency calibration callbacks with securetsc_get_tsc_khz(). Since
the difference between CPU base and TSC frequency does not apply in this
case, the same callback is being used.
[ bp: Carve out from
https://lore.kernel.org/r/20250106124633.1418972-11-nikunj@amd.com ]
Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20250106124633.1418972-11-nikunj@amd.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions