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| author |   Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> | 2022-06-28 21:18:23 +0530 |
|---|---|---|
| committer |   Miquel Raynal <miquel.raynal@bootlin.com> | 2022-06-29 13:36:33 +0200 |
| commit | 7499bfeedb47efc1ee4dc793b92c610d46e6d6a6 (patch) | |
| tree | 310641e8f011af6e8346429381a926b614852604 /scripts/generate_rust_analyzer.py | |
| parent | mtd: rawnand: sm_common: drop unexpected word 'is' in the comments (diff) | |
| download | wireguard-linux-7499bfeedb47efc1ee4dc793b92c610d46e6d6a6.tar.xz wireguard-linux-7499bfeedb47efc1ee4dc793b92c610d46e6d6a6.zip | |
mtd: rawnand: arasan: Update NAND bus clock instead of system clock
In current implementation the Arasan NAND driver is updating the
system clock(i.e., anand->clk) in accordance to the timing modes
(i.e., SDR or NVDDR). But as per the Arasan NAND controller spec the
flash clock or the NAND bus clock(i.e., nfc->bus_clk), need to be
updated instead. This patch keeps the system clock unchanged and updates
the NAND bus clock as per the timing modes.
Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
CC: stable@vger.kernel.org # 5.8+
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220628154824.12222-2-amit.kumar-mahapatra@xilinx.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions