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| author |   Gabriel Fernandez <gabriel.fernandez@foss.st.com> | 2022-06-24 11:27:13 +0200 |
|---|---|---|
| committer |   Alexandre Torgue <alexandre.torgue@foss.st.com> | 2022-07-04 09:10:24 +0200 |
| commit | 78ece8cce1ba0c3f3e5a7c6c1b914b3794f04c44 (patch) | |
| tree | 808fe299aae9c47476e2f70aba87a8bfe0c7eb6f /scripts/generate_rust_analyzer.py | |
| parent | ARM: dts: stm32: fix pwr regulators references to use scmi (diff) | |
| download | wireguard-linux-78ece8cce1ba0c3f3e5a7c6c1b914b3794f04c44.tar.xz wireguard-linux-78ece8cce1ba0c3f3e5a7c6c1b914b3794f04c44.zip | |
ARM: dts: stm32: use the correct clock source for CEC on stm32mp151
The peripheral clock of CEC is not LSE but CEC.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions