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| author |   Andy Yan <andy.yan@rock-chips.com> | 2024-12-14 16:17:02 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2024-12-18 17:38:57 +0100 |
| commit | 7b256880fdb2d7f23393b87bb557090f049e686a (patch) | |
| tree | a638d9be2bdfcbe33220fa8dcd4ca33c79549326 /scripts/generate_rust_analyzer.py | |
| parent | accel/amdxdna: include linux/slab.h (diff) | |
| download | wireguard-linux-7b256880fdb2d7f23393b87bb557090f049e686a.tar.xz wireguard-linux-7b256880fdb2d7f23393b87bb557090f049e686a.zip | |
drm/rockchip: vop2: Set AXI id for rk3588
There are two AXI bus in vop2, windows attached on the same bus must
have a unique channel YUV and RGB channel ID.
The default IDs will conflict with each other on the rk3588, so they
need to be reassigned.
Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Tested-by: Derek Foreman <derek.foreman@collabora.com>
Tested-by: Detlev Casanova <detlev.casanova@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20241214081719.3330518-4-andyshrk@163.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions