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| author |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-07-13 10:42:57 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-07-13 10:44:22 -0700 |
| commit | 7fccd723912702acfc2d75e8f0596982534f7f24 (patch) | |
| tree | ba0de94fae80c24fcf3fa275645cd239b9833b3a /scripts/generate_rust_analyzer.py | |
| parent | riscv: don't warn for sifive erratas in modules (diff) | |
| parent | riscv: dts: microchip: hook up the mpfs' l2cache (diff) | |
| download | wireguard-linux-7fccd723912702acfc2d75e8f0596982534f7f24.tar.xz wireguard-linux-7fccd723912702acfc2d75e8f0596982534f7f24.zip | |
Merge tag 'dt-fixes-for-palmer-5.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into fixes
Microchip RISC-V devicetree fixes for 5.19-rc6
A single fix for mpfs.dtsi:
- The l2 cache controller was never hooked up in the dt, so userspace
is presented with the wrong topology information, so it has been
hooked up.
* tag 'dt-fixes-for-palmer-5.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git:
riscv: dts: microchip: hook up the mpfs' l2cache
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions