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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2022-08-28 10:13:34 +0200 |
|---|---|---|
| committer |   Mauro Carvalho Chehab <mchehab@kernel.org> | 2022-08-30 15:34:10 +0200 |
| commit | 882bda188f691320a001c6adc738c4a7ec102a8d (patch) | |
| tree | eddb499b153baefd7ff31be1408ede3918a9eea9 /scripts/generate_rust_analyzer.py | |
| parent | media: renesas: vsp1: Add VSP1_HAS_NON_ZERO_LBA feature bit (diff) | |
| download | wireguard-linux-882bda188f691320a001c6adc738c4a7ec102a8d.tar.xz wireguard-linux-882bda188f691320a001c6adc738c4a7ec102a8d.zip | |
media: renesas: vsp1: Add support for RZ/G2L VSPD
The RZ/G2L VSPD provides a single VSPD instance. It has the following
sub modules MAU, CTU, RPF, DPR, LUT, BRS, WPF and LIF.
The VSPD block on RZ/G2L SoCs does not have a version register, so
added a new compatible string "renesas,r9a07g044-vsp2" with a data
pointer containing the info structure. Also the reset line is shared
with the DU module.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions