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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2023-02-16 16:20:18 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-03-10 17:07:07 +0100 |
| commit | 88ddf98aa511a5e0c2c76e5dfcf3c6b2581d0e85 (patch) | |
| tree | 552b812be03a9b1c11216bdeeb390ff0255177fe /scripts/generate_rust_analyzer.py | |
| parent | clk: renesas: r8a77995: Fix VIN parent clock (diff) | |
| download | wireguard-linux-88ddf98aa511a5e0c2c76e5dfcf3c6b2581d0e85.tar.xz wireguard-linux-88ddf98aa511a5e0c2c76e5dfcf3c6b2581d0e85.zip | |
clk: renesas: r8a77970: Add Z2 clock
Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3M, which
uses a fixed SYS-CPU divider.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/6a9169e5bc92c2b9549292769a0814e04b9147cf.1676560357.git.geert+renesas@glider.be
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions