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| author |   Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2023-02-11 15:36:54 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2023-03-06 10:42:14 +0100 |
| commit | 8947e5ae9589c57af246cdd149cf469aec5e4d3c (patch) | |
| tree | 5112df6bc83fff6a3fa73e5976104e8cc416d0fa /scripts/generate_rust_analyzer.py | |
| parent | clk: renesas: r8a779g0: Add CSI-2 clocks (diff) | |
| download | wireguard-linux-8947e5ae9589c57af246cdd149cf469aec5e4d3c.tar.xz wireguard-linux-8947e5ae9589c57af246cdd149cf469aec5e4d3c.zip | |
clk: renesas: r8a779g0: Add ISPCS clocks
Add the ISPCS0 and ISPCS1 module clocks, which are used by the ISPCS
modules on the Renesas R-Car V4H (R8A779G0) SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230211143655.3809756-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions