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| author |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-08-25 16:06:49 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-08-25 16:32:39 -0700 |
| commit | 92e55a865bc7b3f89bb8c684f6846651868ee7d7 (patch) | |
| tree | 264436e7c4d757170e4524071d44dbfc4796018e /scripts/generate_rust_analyzer.py | |
| parent | perf: riscv legacy: fix kerneldoc comment warning (diff) | |
| parent | riscv: dts: microchip: mpfs: remove pci axi address translation property (diff) | |
| download | wireguard-linux-92e55a865bc7b3f89bb8c684f6846651868ee7d7.tar.xz wireguard-linux-92e55a865bc7b3f89bb8c684f6846651868ee7d7.zip | |
Merge tag 'dt-fixes-for-palmer-6.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into fixes
Microchip RISC-V devicetree fixes for 6.0-rc3
Two sets of fixes this time around:
- A fix for the interrupt ordering of the l2-cache controller. If the
driver is enabled, it would spam the console /constantly/, rendering
the system useless.
- General cleanup for some bogus properties in the dt, part of my quest
for zero dtbs_check warnings.
On that note, the interrupt ordering adds a dtbs_check warning - but I
considered that fixing the potentially useless system was more of a
priority.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'dt-fixes-for-palmer-6.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git:
riscv: dts: microchip: mpfs: remove pci axi address translation property
riscv: dts: microchip: mpfs: remove bogus card-detect-delay
riscv: dts: microchip: mpfs: remove ti,fifo-depth property
riscv: dts: microchip: mpfs: fix incorrect pcie child node name
riscv: dts: microchip: correct L2 cache interrupts
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions