diff options
| author |   Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> | 2024-06-03 15:02:40 +0800 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2024-06-03 17:41:11 +0530 |
| commit | 9b5fd115e7d5a98b82054cff5c96f6768ee06845 (patch) | |
| tree | 93eb1dbd77743a3834aa9facbc4573b475d3d94c /scripts/generate_rust_analyzer.py | |
| parent | soundwire: bus: add stream refcount (diff) | |
| download | wireguard-linux-9b5fd115e7d5a98b82054cff5c96f6768ee06845.tar.xz wireguard-linux-9b5fd115e7d5a98b82054cff5c96f6768ee06845.zip | |
soundwire: intel_ace2.x: add AC timing extensions for PantherLake
The ACE3 IP used in PantherLake exposes new bitfields in the ACTMCTL
register to better control clocks/delays. These bitfields were
reserved/zero in the ACE2.x IP, to simplify the integration the new
bifields are added unconditionally. The behavior will only be impacted
when the firmware exposes DSD properties to set non-zero values.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20240603070240.5165-1-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions