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| author |   Matt Roper <matthew.d.roper@intel.com> | 2022-07-12 15:05:13 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-07-13 09:22:17 -0700 |
| commit | a5e4a53818ad585416a214b894fdf568443d5293 (patch) | |
| tree | f90229249138297fe64bdaa98faf23c7d60b6c08 /scripts/generate_rust_analyzer.py | |
| parent | drm/i915/ttm: fix 32b build (diff) | |
| download | wireguard-linux-a5e4a53818ad585416a214b894fdf568443d5293.tar.xz wireguard-linux-a5e4a53818ad585416a214b894fdf568443d5293.zip | |
drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms
Accidental use of a "SLICE" macro where a "SUBSLICE" macro was intended
causes the group ID for steering to be calculated incorrectly on
pre-Xe_HP platforms.
Fixes: 9a92732f040a ("drm/i915/gt: Add general DSS steering iterator to intel_gt_mcr")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220712220513.3451794-1-matthew.d.roper@intel.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions