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| author |   Tianling Shen <cnsztl@gmail.com> | 2025-01-19 17:11:54 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2025-02-03 09:14:34 +0100 |
| commit | a6a7cba17c544fb95d5a29ab9d9ed4503029cb29 (patch) | |
| tree | b6711b4d61ada7f387f74836114f032507e3fc1f /scripts/generate_rust_analyzer.py | |
| parent | arm64: dts: rockchip: Fix broken tsadc pinctrl names for rk3588 (diff) | |
| download | wireguard-linux-a6a7cba17c544fb95d5a29ab9d9ed4503029cb29.tar.xz wireguard-linux-a6a7cba17c544fb95d5a29ab9d9ed4503029cb29.zip | |
arm64: dts: rockchip: change eth phy mode to rgmii-id for orangepi r1 plus lts
In general the delay should be added by the PHY instead of the MAC,
and this improves network stability on some boards which seem to
need different delay.
Fixes: 387b3bbac5ea ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS")
Cc: stable@vger.kernel.org # 6.6+
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20250119091154.1110762-1-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions