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| author |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-03-06 16:56:16 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-03-06 16:56:59 +0100 |
| commit | ac409adafb5eb195a3c7f02a58509bf172d6c595 (patch) | |
| tree | 10abfc53d452717faaafeb20309bbcccdec8c33c /scripts/generate_rust_analyzer.py | |
| parent | clk: samsung: Set dev in samsung_clk_init() (diff) | |
| parent | dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks (diff) | |
| download | wireguard-linux-ac409adafb5eb195a3c7f02a58509bf172d6c595.tar.xz wireguard-linux-ac409adafb5eb195a3c7f02a58509bf172d6c595.zip | |
Merge branch 'for-v6.4/clk-exynos850-dt-binding' into next/clk
Merge Devicetree bindings with new Exynos850 clock IDs (headers), used
also by the clock drivers.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions