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| author |   Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-08-26 11:39:22 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-08-31 10:28:19 +0300 |
| commit | addf7efec23af2b67547800aa232d551945e7de2 (patch) | |
| tree | ac2cbb8d44f9a9f27eba6b3714e48093b4a19c11 /scripts/generate_rust_analyzer.py | |
| parent | ARM: at91: pm: fix DDR recalibration when resuming from backup and self-refresh (diff) | |
| download | wireguard-linux-addf7efec23af2b67547800aa232d551945e7de2.tar.xz wireguard-linux-addf7efec23af2b67547800aa232d551945e7de2.zip | |
ARM: dts: at91: sama5d27_wlsom1: specify proper regulator output ranges
Min and max output ranges of regulators need to satisfy board
requirements not PMIC requirements. Thus adjust device tree to
cope with this.
Fixes: 5d4c3cfb63fe ("ARM: dts: at91: sama5d27_wlsom1: add SAMA5D27 wlsom1 and wlsom1-ek")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220826083927.3107272-5-claudiu.beznea@microchip.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions