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| author |   Jon Lin <jon.lin@rock-chips.com> | 2024-12-19 22:22:16 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2025-01-06 13:08:55 +0000 |
| commit | af103eb7d7d881cf6ff7414242bce2d8e394cc32 (patch) | |
| tree | 292675bc6662ed4ece12ea3976066e91edc82a65 /scripts/generate_rust_analyzer.py | |
| parent | spi: cadence-quadspi: Enable SPI_TX_QUAD (diff) | |
| download | wireguard-linux-af103eb7d7d881cf6ff7414242bce2d8e394cc32.tar.xz wireguard-linux-af103eb7d7d881cf6ff7414242bce2d8e394cc32.zip | |
spi: rockchip-sfc: Support sclk_x2 version
SFC after version 8 supports dtr mode, so the IO is the binary output of
the controller clock.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Link: https://patch.msgid.link/20241219142216.2123065-1-jon.lin@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions