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| author |   Jiadong.Zhu <Jiadong.Zhu@amd.com> | 2022-09-15 15:19:20 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-09-27 18:02:58 -0400 |
| commit | b3e45b18e5c40f1f7e5f6383953343f96f963b13 (patch) | |
| tree | f8cdd0fa3818f93432ee73db759a9424d5f037f2 /scripts/generate_rust_analyzer.py | |
| parent | drm/amd/display: fill in clock values when DPM is not enabled (diff) | |
| download | wireguard-linux-b3e45b18e5c40f1f7e5f6383953343f96f963b13.tar.xz wireguard-linux-b3e45b18e5c40f1f7e5f6383953343f96f963b13.zip | |
drm/amdgpu: Correct the position in patch_cond_exec
The current position calulated in gfx_v9_0_ring_emit_patch_cond_exec
underflows when the wptr is divisible by ring->buf_mask + 1.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Jiadong.Zhu <Jiadong.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions