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| author |   Yang Yingliang <yangyingliang@huawei.com> | 2022-06-27 16:08:22 +0800 |
|---|---|---|
| committer |   Alexandre Belloni <alexandre.belloni@bootlin.com> | 2022-07-26 11:29:05 +0200 |
| commit | bb42b7e9e30e7a07b7cb6790a22dc758b0dc123e (patch) | |
| tree | b27317aab773bff9de2f6ef139234e97279de7e6 /scripts/generate_rust_analyzer.py | |
| parent | rtc: zynqmp: Add calibration set and get support (diff) | |
| download | wireguard-linux-bb42b7e9e30e7a07b7cb6790a22dc758b0dc123e.tar.xz wireguard-linux-bb42b7e9e30e7a07b7cb6790a22dc758b0dc123e.zip | |
rtc: rv8803: fix missing unlock on error in rv8803_set_time()
Add the missing unlock before return from function rv8803_set_time()
in the error handling case.
Fixes: f8176e0bb83f ("rtc: rv8803: initialize registers on post-probe voltage loss")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20220627080822.3881072-1-yangyingliang@huawei.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions