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| author |   Garmin.Chang <Garmin.Chang@mediatek.com> | 2023-03-31 20:36:16 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2023-03-31 11:51:21 -0700 |
| commit | bb87c1109ce2f4c947b5b92a1f82ec75f8f969f8 (patch) | |
| tree | 3f109e57a6e7a093d3b8d07744020da5a87084c0 /scripts/generate_rust_analyzer.py | |
| parent | clk: mediatek: Add MT8188 vdosys1 clock support (diff) | |
| download | wireguard-linux-bb87c1109ce2f4c947b5b92a1f82ec75f8f969f8.tar.xz wireguard-linux-bb87c1109ce2f4c947b5b92a1f82ec75f8f969f8.zip | |
clk: mediatek: Add MT8188 vencsys clock support
Add MT8188 vencsys clock controllers which provide clock gate
control for video encoder.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230331123621.16167-15-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions