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| author |   Sunil V L <sunilvl@ventanamicro.com> | 2022-05-27 10:47:40 +0530 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-07-19 16:39:03 -0700 |
| commit | c029e487e7c00e5594a4ae946952605db34e359b (patch) | |
| tree | 7f2a59e456d51f27dd7c48bb8969447e9538ae87 /scripts/generate_rust_analyzer.py | |
| parent | riscv: cpu_ops_sbi: Add 64bit hartid support on RV64 (diff) | |
| download | wireguard-linux-c029e487e7c00e5594a4ae946952605db34e359b.tar.xz wireguard-linux-c029e487e7c00e5594a4ae946952605db34e359b.zip | |
riscv: spinwait: Fix hartid variable type
The hartid variable is of type int but compared with
ULONG_MAX(INVALID_HARTID). This issue is fixed by changing
the hartid variable type to unsigned long.
Fixes: c78f94f35cf6 ("RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method")
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20220527051743.2829940-3-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions