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| author |   Atish Patra <atish.patra@wdc.com> | 2022-02-18 16:46:53 -0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-03-21 14:58:16 -0700 |
| commit | c631121dd16ee57ceb0d6a48e1357382b98350fd (patch) | |
| tree | f01a6d3d86b20261ada750b1c46424e30ec788ef /scripts/generate_rust_analyzer.py | |
| parent | RISC-V: Remove the current perf implementation (diff) | |
| download | wireguard-linux-c631121dd16ee57ceb0d6a48e1357382b98350fd.tar.xz wireguard-linux-c631121dd16ee57ceb0d6a48e1357382b98350fd.zip | |
RISC-V: Add CSR encodings for all HPMCOUNTERS
Linux kernel can directly read these counters as the HPMCOUNTERS CSRs are
accessible in S-mode.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions