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| author |   Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-06-25 15:13:47 +0300 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-06-27 18:17:13 +0200 |
| commit | c7e58843d1e49a6b54d528a8ea34933cafb713f2 (patch) | |
| tree | 64d48efeb8d861ca6844976c70c256c9f3d50918 /scripts/generate_rust_analyzer.py | |
| parent | clk: renesas: r8a779h0: Add Audio clocks (diff) | |
| download | wireguard-linux-c7e58843d1e49a6b54d528a8ea34933cafb713f2.tar.xz wireguard-linux-c7e58843d1e49a6b54d528a8ea34933cafb713f2.zip | |
clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C
Add clock, reset and power domain support for the I2C channels available
on the Renesas RZ/G3S SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240625121358.590547-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions