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| author |   Samuel Holland <samuel.holland@sifive.com> | 2024-03-26 22:45:24 -0700 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2024-03-28 22:40:56 +0000 |
| commit | c90847bcbfb65d0f1c48fcc73a2b3a2d4ceac6a1 (patch) | |
| tree | 35ef25ccad2ec3a49dadb3ca8781c12ab9775baa /scripts/generate_rust_analyzer.py | |
| parent | Linux 6.9-rc1 (diff) | |
| download | wireguard-linux-c90847bcbfb65d0f1c48fcc73a2b3a2d4ceac6a1.tar.xz wireguard-linux-c90847bcbfb65d0f1c48fcc73a2b3a2d4ceac6a1.zip | |
cache: sifive_ccache: Partially convert to a platform driver
Commit 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a
platform driver") broke ccache initialization because the PLIC IRQ
domain is no longer available during an arch_initcall:
[ 0.087229] irq: no irq domain found for interrupt-controller@c000000 !
[ 0.087255] CCACHE: Could not request IRQ 0
Fix this by moving the IRQ handling code to a platform driver.
Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions