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| author |   Conor Paxton <conor.paxton@microchip.com> | 2022-05-17 11:40:58 +0100 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-05-19 16:47:29 -0700 |
| commit | c932edeaf6d6e6cc25088e61c3fcf585c30497c0 (patch) | |
| tree | ded0b63bfc2ab8c0c77b1ecea535fb3ffadecd7c /scripts/generate_rust_analyzer.py | |
| parent | riscv: dts: sifive: fu540-c000: align dma node name with dtschema (diff) | |
| download | wireguard-linux-c932edeaf6d6e6cc25088e61c3fcf585c30497c0.tar.xz wireguard-linux-c932edeaf6d6e6cc25088e61c3fcf585c30497c0.zip | |
riscv: dts: microchip: fix gpio1 reg property typo
Fix reg address typo in the gpio1 stanza.
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Link: https://lore.kernel.org/r/20220517104058.2004734-1-conor.paxton@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions