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| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2022-09-13 17:21:48 +0200 |
|---|---|---|
| committer |   Andi Shyti <andi.shyti@linux.intel.com> | 2022-09-14 13:20:12 +0200 |
| commit | c9424fa1f856eaf09e09a3381fe998dd6f905bfc (patch) | |
| tree | ac5020861889a85d65dc59903edadcfbfe77638e /scripts/generate_rust_analyzer.py | |
| parent | drm/i915: Skip applying copy engine fuses (diff) | |
| download | wireguard-linux-c9424fa1f856eaf09e09a3381fe998dd6f905bfc.tar.xz wireguard-linux-c9424fa1f856eaf09e09a3381fe998dd6f905bfc.zip | |
drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
Even though the initial protocontext we load onto HW has the register
cleared, by the time we save it into the default image, BB_OFFSET has
had the enable bit set. Reclear BB_OFFSET for each new context.
Testcase: igt/i915_selftests/gt_lrc
v2:
Extend it for gen8.
v3:
BB_OFFSET is recorded per engine from Gen9 onwards
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Thomas Hellstrom <thomas.hellstrom@linux.intel.com>
Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/37c67abb3303852f06a570a4360addf52bf941c1.1663081418.git.karolina.drobnik@intel.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions