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| author |   Xianwei Zhao <xianwei.zhao@amlogic.com> | 2024-05-22 16:27:24 +0800 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2024-06-04 10:27:23 +0200 |
| commit | d309989a0a0aff3b8ad5259aa11f119b15336c1a (patch) | |
| tree | 492a35942ef5603e8edc4bd6909d8b7e514eb262 /scripts/generate_rust_analyzer.py | |
| parent | dt-bindings: clock: add Amlogic C3 PLL clock controller (diff) | |
| download | wireguard-linux-d309989a0a0aff3b8ad5259aa11f119b15336c1a.tar.xz wireguard-linux-d309989a0a0aff3b8ad5259aa11f119b15336c1a.zip | |
dt-bindings: clock: add Amlogic C3 SCMI clock controller support
Add the SCMI clock controller dt-bindings for Amlogic C3 SoC family
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Co-developed-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240522082727.3029656-3-xianwei.zhao@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions