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| author |   Peter Griffin <peter.griffin@linaro.org> | 2024-10-31 15:00:33 +0000 |
|---|---|---|
| committer |   Martin K. Petersen <martin.petersen@oracle.com> | 2024-11-06 20:28:26 -0500 |
| commit | d49df3d39244f57957ec744fc5e560939ecb4290 (patch) | |
| tree | 85c2a9bf40c8b34af249e2a5e8387fdab922c649 /scripts/generate_rust_analyzer.py | |
| parent | scsi: ufs: exynos: gs101: Enable clock gating with hibern8 (diff) | |
| download | wireguard-linux-d49df3d39244f57957ec744fc5e560939ecb4290.tar.xz wireguard-linux-d49df3d39244f57957ec744fc5e560939ecb4290.zip | |
scsi: MAINTAINERS: Update UFS Exynos entry
Add myself as a reviewer for ufs-exynos as I'm doing various work in
this driver currently for gs101 SoC and would like to help review
relevant patches.
Additionally add the linux-samsung-soc@vger.kernel.org list as that is
relevant to this driver.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20241031150033.3440894-15-peter.griffin@linaro.org
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions