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| author |   Davidlohr Bueso <dave@stgolabs.net> | 2024-11-15 09:00:32 -0800 |
|---|---|---|
| committer |   Dave Jiang <dave.jiang@intel.com> | 2024-12-10 14:30:51 -0700 |
| commit | da4d8c83358163df9a4addaeba0ef8bcb03b22e8 (patch) | |
| tree | 9ab04fe636e8908aaf1b551530f5d5bdb29d46ae /scripts/generate_rust_analyzer.py | |
| parent | Linux 6.13-rc2 (diff) | |
| download | wireguard-linux-da4d8c83358163df9a4addaeba0ef8bcb03b22e8.tar.xz wireguard-linux-da4d8c83358163df9a4addaeba0ef8bcb03b22e8.zip | |
cxl/pci: Fix potential bogus return value upon successful probing
If cxl_pci_ras_unmask() returns non-zero, cxl_pci_probe() will end up
returning that value, instead of zero.
Fixes: 248529edc86f ("cxl: add RAS status unmasking for CXL")
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/20241115170032.108445-1-dave@stgolabs.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions