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| author |   Philippe Schenker <philippe.schenker@toradex.com> | 2022-09-22 14:43:03 +0200 |
|---|---|---|
| committer |   Neil Armstrong <neil.armstrong@linaro.org> | 2022-09-23 09:19:09 +0000 |
| commit | da73a94fa282f78d485bd0aab36c8ac15b6f792c (patch) | |
| tree | e533ed612c56dfa0c57c915c4bc7de936e12fb35 /scripts/generate_rust_analyzer.py | |
| parent | drm/hisilicon: Add depends on MMU (diff) | |
| download | wireguard-linux-da73a94fa282f78d485bd0aab36c8ac15b6f792c.tar.xz wireguard-linux-da73a94fa282f78d485bd0aab36c8ac15b6f792c.zip | |
drm/bridge: lt8912b: add vsync hsync
Currently the bridge driver does not take care whether or not the display
needs positive/negative vertical/horizontal syncs. Pass these two flags
to the bridge from the EDID that was read out from the display.
Fixes: 30e2ae943c26 ("drm/bridge: Introduce LT8912B DSI to HDMI bridge")
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Acked-by: Adrien Grassein <adrien.grassein@gmail.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220922124306.34729-2-dev@pschenker.ch
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions