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| author |   Srinivas Neeli <srinivas.neeli@xilinx.com> | 2022-08-18 20:36:37 +0530 |
|---|---|---|
| committer |   Wim Van Sebroeck <wim@linux-watchdog.org> | 2022-10-02 12:55:34 +0200 |
| commit | dc1f12b916005e1a1a908fbfcded356634a07038 (patch) | |
| tree | cbf8732e1a62fc1e4ccef660a6a7c418422598d4 /scripts/generate_rust_analyzer.py | |
| parent | watchdog: aspeed_wdt: Reorder output signal register configuration (diff) | |
| download | wireguard-linux-dc1f12b916005e1a1a908fbfcded356634a07038.tar.xz wireguard-linux-dc1f12b916005e1a1a908fbfcded356634a07038.zip | |
dt-bindings: watchdog: Convert Xilinx watchdog bindings to json-schema
Convert Xilinx watchdog bindings to DT schema format using json-schema
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220818150637.815-1-srinivas.neeli@xilinx.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions