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| author |   Horatiu Vultur <horatiu.vultur@microchip.com> | 2022-07-13 21:37:49 +0200 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2022-07-18 11:22:43 +0200 |
| commit | dc62db7138aa9365480254dda4c3e1316b1b1bbc (patch) | |
| tree | 22b94f14dcf5c84c0f2ef399c247102886e3d6b8 /scripts/generate_rust_analyzer.py | |
| parent | MAINTAINERS: Update freescale pin controllers maintainer (diff) | |
| download | wireguard-linux-dc62db7138aa9365480254dda4c3e1316b1b1bbc.tar.xz wireguard-linux-dc62db7138aa9365480254dda4c3e1316b1b1bbc.zip | |
pinctrl: ocelot: Fix pincfg for lan966x
The blamed commit introduce support for lan966x which use the same
pinconf_ops as sparx5. The problem is that pinconf_ops is specific to
sparx5. More precisely the offset of the bits in the pincfg register are
different and also lan966x doesn't have support for
PIN_CONFIG_INPUT_SCHMITT_ENABLE.
Fix this by making pinconf_ops more generic such that it can be also
used by lan966x. This is done by introducing 'ocelot_pincfg_data' which
contains the offset and what is supported for each SOC.
Fixes: 531d6ab36571 ("pinctrl: ocelot: Extend support for lan966x")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220713193750.4079621-2-horatiu.vultur@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions