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| author |   Andre Przywara <andre.przywara@arm.com> | 2022-05-04 18:07:36 +0100 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2022-05-14 01:07:08 +0200 |
| commit | e199975b775a37750903025915f7bc0ccda829e5 (patch) | |
| tree | b5d859a4d5513a4215e6ed746f9e5a7b309a591e /scripts/generate_rust_analyzer.py | |
| parent | pinctrl: sunxi: fix f1c100s uart2 function (diff) | |
| download | wireguard-linux-e199975b775a37750903025915f7bc0ccda829e5.tar.xz wireguard-linux-e199975b775a37750903025915f7bc0ccda829e5.zip | |
pinctrl: sunxi: f1c100s: Fix signal name comment for PA2 SPI pin
The manual describes function 0x6 of pin PA2 as "SPI1_CLK", so change
the comment to reflect that.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220504170736.2669595-1-andre.przywara@arm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions