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| author |   Pawel Laszczak <pawell@cadence.com> | 2024-09-02 11:09:16 +0000 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-09-03 10:03:54 +0200 |
| commit | e2940928115e83d707b21bf00b0db7d6c15f8341 (patch) | |
| tree | a341294a4036cef19fd985b872a21fe992e6eb75 /scripts/generate_rust_analyzer.py | |
| parent | usb: dwc3: core: update LC timer as per USB Spec V3.2 (diff) | |
| download | wireguard-linux-e2940928115e83d707b21bf00b0db7d6c15f8341.tar.xz wireguard-linux-e2940928115e83d707b21bf00b0db7d6c15f8341.zip | |
usb: cdns2: Fix controller reset issue
Patch fixes the procedure of resetting controller.
The CPUCTRL register is write only and reading returns 0.
Waiting for reset to complite is incorrect.
Fixes: 3eb1f1efe204 ("usb: cdns2: Add main part of Cadence USBHS driver")
cc: stable@vger.kernel.org
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Link: https://lore.kernel.org/r/PH7PR07MB9538D56D75F1F399D0BB96F0DD922@PH7PR07MB9538.namprd07.prod.outlook.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions