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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-09-18 17:44:44 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-10-09 19:16:16 +0300 |
| commit | e6b72ba9c1ea4b5556027d502316a8362f1a9e11 (patch) | |
| tree | 77cac717dfc7bbb2a0039cf00d3594f14cfd9412 /scripts/generate_rust_analyzer.py | |
| parent | drm/i915: Enable fp16 + CCS on TGL+ (diff) | |
| download | wireguard-linux-e6b72ba9c1ea4b5556027d502316a8362f1a9e11.tar.xz wireguard-linux-e6b72ba9c1ea4b5556027d502316a8362f1a9e11.zip | |
drm/i915: Drop GEN12_MC_CCS check from skl_plane_max_width()
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS is tgl+ only, so checking for
it in skl_plane_max_width() (which only applies to pre-glk hardware)
is pointless.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240918144445.5716-7-ville.syrjala@linux.intel.com
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions