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author | 2022-08-01 10:04:00 -0700 | |
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committer | 2022-08-01 10:04:00 -0700 | |
commit | ecf9b7bfea60ca816b2b44716e3f1dde148ea196 (patch) | |
tree | 32e272d2a7060ea421c0ba303a0038bae0e69e92 /scripts/generate_rust_analyzer.py | |
parent | Merge tag 'x86_misc_for_v6.0_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (diff) | |
parent | x86/extable: Fix ex_handler_msr() print condition (diff) | |
download | wireguard-linux-ecf9b7bfea60ca816b2b44716e3f1dde148ea196.tar.xz wireguard-linux-ecf9b7bfea60ca816b2b44716e3f1dde148ea196.zip |
Merge tag 'x86_core_for_v6.0_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 core updates from Borislav Petkov:
- Have invalid MSR accesses warnings appear only once after a
pr_warn_once() change broke that
- Simplify {JMP,CALL}_NOSPEC and let the objtool retpoline patching
infra take care of them instead of having unreadable alternative
macros there
* tag 'x86_core_for_v6.0_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/extable: Fix ex_handler_msr() print condition
x86,nospec: Simplify {JMP,CALL}_NOSPEC
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions