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| author |   William Zhang <william.zhang@broadcom.com> | 2022-08-01 12:44:47 -0700 |
|---|---|---|
| committer |   Florian Fainelli <f.fainelli@gmail.com> | 2022-08-15 09:35:53 -0700 |
| commit | ed93a068f3b3ac22423edfaf8509eaafedf3efc0 (patch) | |
| tree | 0a86e4d9252d2e7943978bdf1226d131b7dccbc4 /scripts/generate_rust_analyzer.py | |
| parent | ARM: dts: bcmbca: bcm63178: clean up psci node (diff) | |
| download | wireguard-linux-ed93a068f3b3ac22423edfaf8509eaafedf3efc0.tar.xz wireguard-linux-ed93a068f3b3ac22423edfaf8509eaafedf3efc0.zip | |
ARM: dts: bcmbca: bcm63178: fix interrupt controller node
Add the missing gic registers and interrupts property to the gic node.
Fixes: fc85b7e64acb ("ARM: dts: add dts files for bcmbca soc 63178")
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20220801194448.29363-3-william.zhang@broadcom.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions