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| author |   Aniket <aniketmaurya@google.com> | 2024-07-08 06:21:02 +0000 |
|---|---|---|
| committer |   Alexandre Belloni <alexandre.belloni@bootlin.com> | 2024-07-26 14:21:30 +0200 |
| commit | effd21743c39a6535f204812006054fa172e4313 (patch) | |
| tree | 1e60badc7fe263298d772a7ca4379e9fe1a17817 /scripts/generate_rust_analyzer.py | |
| parent | i3c: dw: Save timing registers and other values (diff) | |
| download | wireguard-linux-effd21743c39a6535f204812006054fa172e4313.tar.xz wireguard-linux-effd21743c39a6535f204812006054fa172e4313.zip | |
i3c: dw: Add some functions for reusability
Separate logic for setting intr/thld registers in a func.
Also modify enable function to take care of setting all fields in DEVICE_CTRL.
These functions can be reused later for power management.
Signed-off-by: Aniket <aniketmaurya@google.com>
Link: https://lore.kernel.org/r/20240708062103.3296587-3-aniketmaurya@google.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions