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| author |   Jiang Jian <jiangjian@cdjrlc.com> | 2022-06-22 14:32:31 +0800 |
|---|---|---|
| committer |   Guenter Roeck <linux@roeck-us.net> | 2022-06-29 14:02:08 -0700 |
| commit | f0aa153b6ce8018a052d9c05dc1b8483ac3a0f1a (patch) | |
| tree | a7a93ba680d267c4246a4fab2d0fb442891320b1 /scripts/generate_rust_analyzer.py | |
| parent | hwmon: (occ) Prevent power cap command overwriting poll response (diff) | |
| download | wireguard-linux-f0aa153b6ce8018a052d9c05dc1b8483ac3a0f1a.tar.xz wireguard-linux-f0aa153b6ce8018a052d9c05dc1b8483ac3a0f1a.zip | |
hwmon: (pmbus/ucd9200) fix typos in comments
Drop the redundant word 'the' in the comments following
/*
* Set PHASE registers on all pages to 0xff to ensure that phase
* specific commands will apply to all phases of a given page (rail).
* This only affects the READ_IOUT and READ_TEMPERATURE2 registers.
* READ_IOUT will return the sum of currents of all phases of a rail,
* and READ_TEMPERATURE2 will return the maximum temperature detected
* for the [the - DROP] phases of the rail.
*/
Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com>
Link: https://lore.kernel.org/r/20220622063231.20612-1-jiangjian@cdjrlc.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions