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| author |   Xiu Jianfeng <xiujianfeng@huawei.com> | 2022-10-02 10:19:11 +0530 |
|---|---|---|
| committer |   Anup Patel <anup@brainfault.org> | 2022-10-02 10:19:11 +0530 |
| commit | f493cdc92d9b9e9a0db0a9049609457e43a56066 (patch) | |
| tree | d1716d4d4cb241bc466617a2d622fc51d4a6282a /scripts/generate_rust_analyzer.py | |
| parent | RISC-V: KVM: Expose Zicbom to the guest (diff) | |
| download | wireguard-linux-f493cdc92d9b9e9a0db0a9049609457e43a56066.tar.xz wireguard-linux-f493cdc92d9b9e9a0db0a9049609457e43a56066.zip | |
RISC-V: KVM: add __init annotation to riscv_kvm_init()
The riscv_kvm_init() is a module_init entry so let us add __init
annotation to it.
Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions