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| author |   Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2025-01-17 08:09:09 +0100 |
|---|---|---|
| committer |   Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2025-01-22 20:55:01 +0000 |
| commit | f520fab580c9179bacc432f3a3bf1eada73fdfcc (patch) | |
| tree | 291121a3117af02ca4dc82d6b38e43f40891173e /scripts/generate_rust_analyzer.py | |
| parent | ARM: 9433/2: implement cacheinfo support (diff) | |
| download | wireguard-linux-f520fab580c9179bacc432f3a3bf1eada73fdfcc.tar.xz wireguard-linux-f520fab580c9179bacc432f3a3bf1eada73fdfcc.zip | |
ARM: 9440/1: cacheinfo fix format field mask
Fix C&P error left unnoticed during the reviews. The FORMAT field spans
over bits 29-31, not 24-27 of the CTR register.
Closes: https://lore.kernel.org/linux-arm-msm/01515ea0-c6f0-479f-9da5-764d9ee79ed6@samsung.com/
Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support")
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions