diff options
| author |   Leo Chen <sancchen@amd.com> | 2023-04-26 16:02:28 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-05-11 01:08:00 -0400 |
| commit | f57fa0f23d9707747272b0d09af8b93b19cf8ee4 (patch) | |
| tree | 0fff2b1377a8a85e931d7c02f81100400b293536 /scripts/generate_rust_analyzer.py | |
| parent | drm/amd/pm: parse pp_handle under appropriate conditions (diff) | |
| download | wireguard-linux-f57fa0f23d9707747272b0d09af8b93b19cf8ee4.tar.xz wireguard-linux-f57fa0f23d9707747272b0d09af8b93b19cf8ee4.zip | |
drm/amd/display: Add symclk workaround during disable link output
[Why & How]
This is originally a change (9c75891f) in DCN32 because of the lack
of interface to set TX while keeping symclk on. Adding this workaround
to DCN314 will resolve the current issue.
Fixes: 9c75891feef0 ("drm/amd/display: rework recent update PHY state commit")
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Leo Chen <sancchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions