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| author |   Michal Simek <michal.simek@amd.com> | 2025-01-16 15:55:46 +0100 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2025-01-16 15:20:41 +0000 |
| commit | fee89ddd76e45841a2b01d87b481bc02483f4572 (patch) | |
| tree | 16cf1edfa46f234b995375f107680425a525ef35 /scripts/generate_rust_analyzer.py | |
| parent | ASoC: dapm: add support for preparing streams (diff) | |
| download | wireguard-linux-fee89ddd76e45841a2b01d87b481bc02483f4572.tar.xz wireguard-linux-fee89ddd76e45841a2b01d87b481bc02483f4572.zip | |
ASoC: xilinx: xlnx_spdif: Simpify using devm_clk_get_enabled()
Clock handling can be very simlified with using devm_clk_get_enabled() as
was done by commit 8d2aaf4382b7 ("gpio: zynq: Simplify using
devm_clk_get_enabled()").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://patch.msgid.link/90075f57ceff7cdf958d0d146f46f50661335236.1737039345.git.michal.simek@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions