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| author |   Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2024-10-17 21:04:47 +0300 |
|---|---|---|
| committer |   Krzysztof Wilczyński <kwilczynski@kernel.org> | 2024-11-02 14:32:28 +0000 |
| commit | d38cc57c14ff9590e03da77987217eca19ea350d (patch) | |
| tree | 0c9ef1beec54c9ecbb8489d9cbb1354db02a753c /scripts/lib/kdoc/kdoc_files.py | |
| parent | dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only (diff) | |
| download | wireguard-linux-d38cc57c14ff9590e03da77987217eca19ea350d.tar.xz wireguard-linux-d38cc57c14ff9590e03da77987217eca19ea350d.zip | |
dt-bindings: PCI: qcom,pcie-sm8550: Add SAR2130P compatible
On the Qualcomm SAR2130P platform the PCIe host is compatible with the
DWC controller present on the SM8550 platorm, just using one additional
clock.
Link: https://lore.kernel.org/r/20241017-sar2130p-pci-v1-1-5b95e63d9624@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'scripts/lib/kdoc/kdoc_files.py')
0 files changed, 0 insertions, 0 deletions