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authorBiju Das <biju.das.jz@bp.renesas.com>2025-02-24 13:11:26 +0000
committerThomas Gleixner <tglx@linutronix.de>2025-02-26 11:59:50 +0100
commit76c3b774734feb8224b78721e0c67a54760a75c5 (patch)
tree0b22f107e2e9d6625fb13336c5b2425153be9db3 /scripts/lib/kdoc/kdoc_re.py
parentirqchip/renesas-rzv2h: Add field_width to struct rzv2h_hw_info (diff)
downloadwireguard-linux-76c3b774734feb8224b78721e0c67a54760a75c5.tar.xz
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irqchip/renesas-rzv2h: Update TSSR_TIEN macro
On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. Replace the macro ICU_TSSR_TIEN(n)->ICU_TSSR_TIEN(n, _field_width) for supporting both these SoCs. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/all/20250224131253.134199-11-biju.das.jz@bp.renesas.com
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